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Triple Timer Module
9.3.1.4 Timer Event Counter (Mode 3)
Bit Settings
Mode Characteristics
TC3
0
TC2
0
TC1
1
TC0
1
Mode
3
Name
Event Counter
Function
Timer
TIO
Input
Clock
External
In Mode 3, the timer counts external events and issues an interrupt (if interrupt enable bits are set)
when the timer counts a preset number of events. The timer clock signal can be taken from either
the TIO input signal or the prescaler clock output. If an external clock is used, it must be
internally synchronized to the internal clock, and its frequency must be less than the DSP56311
internal operating frequency divided by 4. The value of the TCSR[INV] bit determines whether
low-to-high (0 to 1) transitions or high-to-low (1 to 0) transitions increment the counter. If the
INV bit is set, high-to-low transitions increment the counter. If the INV bit is cleared,
low-to-high transitions increment the counter.
When the counter matches the value contained in the TCPR, TCSR[TCF] is set and a compare
interrupt is generated if the TCSR[TCIE] bit is set. If the TCSR[TRM] bit is set, the counter is
loaded with the value of the TLR when the next timer clock is received, and the count is resumed.
If the TCSR[TRM] bit is cleared, the counter continues to increment on each timer clock. This
process repeats until the timer is disabled.
Mode 3 (internal clock): TRM = 1
N = write preload
first event
M = write compare
TE
if clock source
is from TIO pin,
Clock
(TIO pin or prescale CLK)
TIO < CPUCLK + 4
TLR
N
Counter (TCR)
0
N
N+1
M
N
N+1
TCPR
M
TCF (Compare Interrupt if TCIE = 1)
interrupts every
M - N clock
periods
NOTE: If INV = 1, counter is clocked on 1-to-0 clock transitions, instead of 0-to-1 transitions.
Figure 9-9. Event Counter Mode, TRM = 1
DSP56311 User’s Manual, Rev. 2
9-10
Freescale Semiconductor
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